The present invention relates to a semiconductor memory device.
FIG. 2 is a circuit diagram illustrating an array 200 of dynamic random-access memory (DRAM) cells 100, each including two transistors 110a and 101b and one capacitor 102, and its peripheral circuits for a known semiconductor memory device. In each of the memory cells 100 shown in FIG. 2, the first transistor 110a has its gate, drain and source connected to first word line WL1a, first bit line BL1a and storage node SN, respectively. The second transistor 101b has its gate, drain and source connected to second word line WL1b, second bit line BL1b and storage node SN, respectively. One of the two electrodes of the capacitor 102 is connected to the storage node SN, while the other electrode thereof is used as a cell plate.
Thus, each memory cell 100 includes two transistors 101a and 101b that are independently controllable with respect to one capacitor 102. Accordingly, the same memory cell 100 can be accessed through two different ports, i.e., a port including the first word line WL1a, first transistor 101a and first bit line BL1a and a port including the second word line WL1b, second transistor 101b and second bit line BL1b. In other words, a memory cell 100 of this type realizes interleaved access.
A memory cell 100 of this type will be herein called a xe2x80x9c2Tr1C memory cellxe2x80x9d. Also, the port accessing a memory cell 100 by way of the first transistor 101a will be herein called an xe2x80x9cA-portxe2x80x9d while the port accessing the same memory cell 100 by way of the second transistor 101b will be herein called a xe2x80x9cB-portxe2x80x9d.
A synchronous DRAM (SDRAM) using normal memory cells, each including one transistor and one capacitor, has multiple banks and can transfer input or output data continuously by performing an interleaved operation between or among those banks. However, where multiple memory cells belonging to the same bank should be accessed successively, the SDRAM needs a precharge/equalize interval. Accordingly, the transfer of data should be stopped for this interval.
On the other hand, a semiconductor memory device including the 2Tr1C memory cells 100 performs a burst mode operation using one of the two ports while the other port is in standby mode. Accordingly, the device can perform a precharge operation using the latter port. In addition, if a command is input in view of the length of burst data and the latency of data transferred, then the device can consecutively input or output data to/from even multiple memory cells belonging to the same bank.
FIG. 6 is a timing diagram illustrating how the semiconductor memory device including the 2Tr1C memory cells 100 reads out burst data. Suppose this memory device inputs addresses by a non-multiplexer method and has a latency of 2, a random-access cycle number of 4 and a burst length of 4. In the example illustrated in FIG. 6, the first and second types of word lines activated are identified by WLa and WLb, respectively.
As shown in FIG. 6, a read command RD is input at a time T1. In response, the first word line WL1a, for example, is activated and data is read out through the A-port including the first bit lines BL1a, BL3a, BL5a and so on. As a result, data bits Da0 through Da3 are output consecutively between times T3 and T7.
At a time T5 when a next command can be input, a read command RD is input again. In response, the second word line WL1b, for example, is activated and data is read out through the B-port including the second bit lines BL1b, BL3b, BL5b and so on. As a result, data bits Db0 through Db3 are output consecutively between times T7 and T11.
The second bit lines BL1b and so on, included in the B-port, are precharged and equalized while the data is read out through the A-port. Accordingly, as soon as the burst data has been read out through the A-port, the data can be read out through the B-port. In this manner, data can be transferred continuously.
Thus, while the memory device is precharging using one of the ports, the device can access the memory cells 100 through the other port. As a result, this memory device requires no apparent precharge interval and can perform read and write operations at a high speed.
Even a semiconductor memory device with these two ports also needs a refresh operation. Normally, the refresh operation should be performed while no memory cells are accessed (i.e., no data is read out or written from/on any memory cells). Thus, it has been necessary to design a system with the refresh timings taken into account or to suspend the data input/output operation for the refresh interval. As a result, the system might have had its configuration overly complicated. Furthermore, the refresh operation might also prevent the user from taking full advantage of the performance a chip originally has.
It is therefore an object of the present invention to enable a semiconductor memory device to transfer data continuously without stopping its read or write operation for the purpose of refreshing.
Specifically, a semiconductor memory device according to the present invention includes memory array, first and second rows of sense amplifiers and selector. The memory array has first and second ports. The first and second rows are associated with the first and second ports, respectively. Responsive to a port selection signal, the selector selects the first or second port to transfer burst data therethrough, and couples the first or second row, associated with the port selected, to a data input or output circuit. If the selector has selected the first port, the device performs a refresh operation on the memory array using the second row while transferring the burst data through the first port. On the other hand, if the selector has selected the second port, the device performs the refresh operation on the memory array using the first row while transferring the burst data through the second port.
According to the present invention, while the memory device is transferring burst data through one of the two ports, the device can perform a refresh operation using the other port. Thus, there is no need to stop the data transfer for the refreshing purposes and the burst data can be transferred continuously at a high speed.
In one embodiment of the present invention, the memory device preferably further includes a command generator for generating the port selection signal on receiving a read or write command. Then, every time the memory device receives a read or write command, the device can transfer the burst data through one of the two ports that has just gone through the refresh operation.
In this particular embodiment, the memory device preferably further includes a refresh timer and a refresh control circuit. The refresh timer preferably outputs a refresh request signal. On receiving the read or write command, the command generator preferably generates a command detection signal. In response to the refresh request signal and the command detection signal, the refresh control circuit preferably generates a refresh command to refresh the memory array. Then, there is no need to control the refresh timings externally.
Specifically, the refresh control circuit preferably includes means for setting a refresh enabled interval and a refresh controller. The setting means generates a refresh enable signal, indicating an interval during which the refresh operation is enabled, in response to the command detection signal. The refresh controller generates the refresh command in response to the refresh enable signal and the refresh request signal. Then, no refresh commands will be generated in an interval in which the refresh operation is disabled.
In this case, the memory device preferably transfers the burst data of a predetermined burst length through either the first or second port selected on receiving the read or write command.
More specifically, the setting means preferably includes a counter and a decoder. Preferably, the counter is reset responsive to the command detection signal, counts the number of clock pulses applied to control the operation of the semiconductor memory device and outputs the number as a count. When the count reaches a predetermined value, the decoder preferably asserts and outputs the refresh enable signal. In such an embodiment, it is possible to control the refresh timing appropriately and synchronously with a clock pulse.
In still another embodiment, the refresh control circuit preferably further includes a latch that latches the refresh request signal and then outputs it to the refresh controller. The output of the latch is preferably cleared in response to the refresh command.
In yet another embodiment, the memory array preferably includes a plurality of memory cells and first and second groups of bit lines. Each of the memory cells preferably includes a capacitor for storing data thereon and first and second transistors. The first and second transistors preferably have their source connected to one electrode of the capacitor. Each said bit line of the first group preferably couples drains of the first transistors, included in associated ones of the memory cells, to the first row of sense amplifiers. Each said bit line of the second group preferably couples drains of the second transistors, included in associated ones of the memory cells, to the second row of sense amplifiers.